the 32°C issue wasnt from my personal experience, just quoted a post on a old thread.
and even with good airflow in summer its very hot sometimes ambiant air could be around 40°C in my country.
thats why im looking for a trick to increase this treshold, dont know if increase TRFC could help.
@Veii recommended +1 on TRDWR or increasing TRP reduce needed voltage then reduce heat.
but not sure if timings affect the treshold temp.
tRP ~ row precharge time.
The minimum number of clock cycles required between issuing the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is tRP + tRCD + CL.”
If the wrong row is open (“page miss”), it needs to be closed (precharged), then the next needs to be opened, then the column within the row needs to be accessed. This therefore takes tRP + tRCD + CL time
Same as tRC
The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.
Every ROW ACTivate command needs it's corresponding PRE charge command
tRFC goes together with that row of 3 (well usually also tRTP but let's ingore that)
Voltage isn't kept indefinitely. You lose charge
And more voltage is sometimes needed to cover shorter burst operations ~ lower timings
In a purely logical sense, slower timings might recharge slower, but are also discharged slower.
Which also logically need a slower tRFC (Timing~Row Refresh Cycle).
The same goes for tRP ~ this one is unique on it's own and very flexible.
Heat will discharge DRAM faster ~ soo your unified answer would be "lower temps"
And as heat increases, soo does also voltage leakage and charge "loss"
It's combatable with simply a longer time to (p)recharge and just simply slower timings
It's also combatable with fluid transitions, soo no charge is wasted anywhere (looking at tRC=tRAS+tRP)
While tRC is flexible , tRAS is not
Row Active Time:
tRAS is the number of clock cycles taken between a bank active command and issuing the precharge command.
Pretty much increasing tRP will fix your issue,or wasting cycles on tRC (increasing it) will also hide "corpses" (of bad timings)
But it's more inteligent to work on the root of the issue = transition delay
Slowing down the cycles by tRRD_ and tWTR_ between rows and collums, and so it's corresponding tFAW
(Intel Naming= tRRDR & tRRDD)
Already does the most difference between instability and stability ~ as long as remain transitions are clean
But if you for example take the easier cheating route and just let everything pile up and wait till tRC finally zZZ is over
Well you might hide corpses,
but your latency will show it and your stability & performance will be . . . how do i say it ~ "variable"
EDIT:
Just increasing tRCD also does fix your problems, but that's i guess not the question. By using simply slower timings
At the end it's quite simple:
Instability between timing-transition comes from loss of charge.
Loss of charge is fixed by more charge
Loss of charge happens faster by higher heat
Higher heat-generations happens with higher voltage 🤭
