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Hey all looking for some help as how I might improve my ram latency. I can't seem to get my latency below 60ns. I am running 4x8 Gskill F4-3600C15-8GTZ. My timings are in the image below. System is stable with these timings, but I feel like I can squeeze out more. Currently I am unable to boot if I try and push the memory & F-clock to anything greater than 1866mhz. I also have to keep Gear down mode enabled or else the system gets unstable. Maybe I have hit my ram wall? Maybe I am hitting the limits of what my motherboard can do? I am not sure. Looking for some advice as how I can further tune my memory.
CPU: 5900x
Motherboard: Gigabyte x570 ultra F31 bios
Ram: 4x8 Gskill F4-3600C15-8GTZ
View attachment 2468789
I'd put more juice on that VSOC, it's only 25mV above VDDG.
Try with 1150mV.
 
Hey all looking for some help as how I might improve my ram latency. I can't seem to get my latency below 60ns.
View attachment 2468789
Go couple of pages back in this thread to read :)
4 Key mistakes you do:
  • Your RTT values are for single rank 2x8 kit setup, and then only near 1.46v / they are wrong for higher voltage and absolutely wrong for 4 dimms
  • your voltages overall are far to high , lower them (read the older posts before you)
  • timings are a bit of a mess . tFAW = 4* tRRD_S not 5 not 3 , maybe 8 would work. / tWRWR & tRDRD SD + DD are wrong, use a stepping of 2 between them , not a 1 = 1-4-4-1-6-6 for example
  • tRFC 1-2-4 should be used on Vermeer, and tCKE is used ~ even with GDM on / try tCKE 16 for b-dies

Overall voltage issues aside
your timings are harsh, and i am sure you didn't check the PCB version of each of your kit
It can be that these are on a different PCB (both sets) and just not plugged in the correct place
Yes, your timings are harsh ~ try something a bit more tame and first push FCLK & fix the voltages ,before you push both
Especially when 5xxx series does autocorrect on everything and slow itself down to prevent crashes

This two docs have "patterns" for you to copy
&

CAD_BUS you should start with 40-20-20-20
maybe go up to 60-20-20-20 with 4 dimms

RTT is up to you to figure out with 4 dimms
try maybe if 7 / 0 / 6 works also for 4 dimms ~ but this one requires you to move near 1.47+ VDIMM , even 1.48+
Figuring out which PCB these kits are on, running a lose 16-16-16 set to figure out voltage & procODT
all these should be your first priority before you land in a deep rabbit hole of autocorrection
Crashing Vermeer is very very hard , but making it unhappy is as easy as just 20mV wrong voltage ~somewhere~

EDIT:
I would also try to CMOS reset & go back to 1800FCLK
There are bugs where 2:1 mode is turned on in the hidden
61ns on Vermeer, equals about 71-72ns on Matisse
Either something is strongly autocorrecting and slowing itself down
Or you have the 10ns 2:1 mode penalty in there

It's a bit too slow for your used timings - soo something is clearlywrong
Also F31f is a bit slow - visible on t he old SMU 56.40
You can stay on this - if gigabyte also has no FCLK limits on it
Or try your luck and update to F31o or higher ~ just with the likelyhood of being limited beyond 1900FCLK

UPDATE1: going back to my new kit for testing (2x8) How long should I run y-cruncher for??
3 passed loops with all tests. 3x 18min
at best 4x18

it should already FFT & N32 crash on the first loop if voltages are wrong
or on the 2nd loop if your VRMs droop too much by heat ~ as an LLC issue
 
@berger0 There's an app called power settings explorer that allows you to see the hidden registry settings of things like processor power management. Sorry I don't have a link for it. If you set Processor idle disable to disable idle you can gain up to a 1ns reduction in latency.

@Veii I'm back to testing 4x8

ProcODT @ 43.6ohm
RttNom RZQ/5
RttWr Off
RttPark RZQ/5
vSOC to 1.062 and it hits a droop of 1.0375v most of the time, sometimes hits 1.043v
vDDG to 1.029 which droops to 1.0271v.

The rest is the same as in the the Zen timings screen shot I posted a page back.

I'm on the second loop/iteration of y-cruncher at per how you suggested with All tests.
I've had HWiNFO64 open for 2+hrs. WHEA errors: CPU Bus/Interconnect Errors - 1 during second loop/iteration

UPDATE: trying vDDG @ 1.031 which droops to 1.0300v

UPDATE1: it seems the increase of vDDG both CCD & IOD to 1.031 helped
Text Photograph Colorfulness Style Line
 
@berger0 There's an app called power settings explorer that allows you to see the hidden registry settings of things like processor power management. Sorry I don't have a link for it. If you set Processor idle disable to disable idle you can gain up to a 1ns reduction in latency.

@Veii I'm back to testing 4x8

ProcODT @ 43.6ohm
RttNom RZQ/5
RttWr Off
RttPark RZQ/5
vSOC to 1.043 and it hits a droop of 1.0375v most of the time
vDDG to 1.029 which droops to 1.0271v.

The rest is the same as in the the Zen timings screen shot I posted a page back.

I'm on the second loop/iteration of y-cruncher at per how you suggested with All tests.
I've had HWiNFO64 open for 2+hrs. WHEA errors: CPU Bus/Interconnect Errors - 1
This it?

 
@KedarWolf Yes, that's it. Someone made a tweaked version of it that places the windows differntly and gives descriptions of any highlighted key.. both are essentially the same.
 
@berger0 There's an app called power settings explorer that allows you to see the hidden registry settings of things like processor power management. Sorry I don't have a link for it. If you set Processor idle disable to disable idle you can gain up to a 1ns reduction in latency.

@Veii I'm back to testing 4x8

ProcODT @ 43.6ohm
RttNom RZQ/5
RttWr Off
RttPark RZQ/5
vSOC to 1.062 and it hits a droop of 1.0375v most of the time, sometimes hits 1.043v
vDDG to 1.029 which droops to 1.0271v.

The rest is the same as in the the Zen timings screen shot I posted a page back.

I'm on the second loop/iteration of y-cruncher at per how you suggested with All tests.
I've had HWiNFO64 open for 2+hrs. WHEA errors: CPU Bus/Interconnect Errors - 1 during second loop/iteration

UPDATE: trying vDDG @ 1.031 which droops to 1.0300v

UPDATE1: it seems the increase of vDDG both CCD & IOD to 1.031 helped
View attachment 2468832
I did the Disable Idle and my read/write/copy was lower and my latency shot up from 61.9 to 90ms on my 3950x. :(
 
I did the Disable Idle and my read/write/copy was lower and my latency shot up from 61.9 to 90ms on my 3950x. :(
Are you using a timer resolution tool? I am not. My Matisse latency went from 65.4 to 64.3ns and I was able to reproduce it. Only thing I tried was 'disable idle'
 
Are you using a timer resolution tool? I am not. My Matisse latency went from 65.4 to 64.3ns and I was able to reproduce it. Only thing I tried was 'disable idle'
No, I'm not. I might have disabled HPET though, don't remember for sure.
 
@KedarWolf Not sure why that's happening.

@Veii After the successful y-cruncher test, I played a few games. 3hrs later I rebooted, ran P95 Large FFTs and 1 core crashed immediately. Raised the vDDG IOD & CCD to 1.0330v and then y-cuncher crashed on HNT first loop. Rebooted and set the vSOC to 1.075v which droops to 1.050 and I'm running y-cruncher again.. I'll update more on this later, but it seems rebooting my machine destabilizes things..
 
@Veii After the successful y-cruncher test, I played a few games. 3hrs later I rebooted, ran P95 Large FFTs and 1 core crashed immediately. Raised the vDDG IOD & CCD to 1.0330v and then y-cuncher crashed on HNT first loop. Rebooted and set the vSOC to 1.075v which droops to 1.050 and I'm running y-cruncher again.. I'll update more on this later, but it seems rebooting my machine destabilizes things..
This might be hard to track for you
But is there any chance you can find out which ABL and SMU you are on ?
SMU is read out via ZenTimings - but ABL and the rest is only written on the AMD PBS menu - which is next to CBS
Usually in the same place where you can change PCIe Gen

I was pushing today the system a bit again
Got up to 2133FCLK ~ 2167 crashes a bit
Saved couple of pictures to showcase how worse auto correction can be

But my main intention with this post is:
ABL 09284010 & SMU 56.34 (known as Patch-C) ~ have completely broken memory training
I somehow barely got 1900FCLK to post ~ about 1 out of 6 to 7 tries & it was stable afterwards lol

There is a new ABL* that works on current SMU (gigabyte beta bios)
- which allows the utilization of the 2nd CCD (at least for L3 cache)
Apparantly atleast my 5600X is a full dual 8 CCD ~ 16core, with disabled CCD and two less cores
It's recognized as such one lol
This explains to me well why they cost more than usual
Fully no idea how to unlock it - but SMU reads it technically out as a 5950X :unsure:

* looking into how to transplant that ABL over ~ because ASRock doesn't do much, at all tbh
** if i figure it out ~ it should be replicatable to other boards with SMU 56.34,
which then just need AMD CBS -> PHY unlock to fix broken memory training
EDIT:
Or we could just grab the SMU 56.37 from ASUS boards 🤭
But i like this open ABL 09084010 ~ which has no! FCLK Lock
Only buggy SMU which goes to 2:1 mode on 2100 and 4:1 mode on 2134
 
Go couple of pages back in this thread to read :)
4 Key mistakes you do:
  • Your RTT values are for single rank 2x8 kit setup, and then only near 1.46v / they are wrong for higher voltage and absolutely wrong for 4 dimms
  • your voltages overall are far to high , lower them (read the older posts before you)
  • timings are a bit of a mess . tFAW = 4* tRRD_S not 5 not 3 , maybe 8 would work. / tWRWR & tRDRD SD + DD are wrong, use a stepping of 2 between them , not a 1 = 1-4-4-1-6-6 for example
  • tRFC 1-2-4 should be used on Vermeer, and tCKE is used ~ even with GDM on / try tCKE 16 for b-dies

Overall voltage issues aside
your timings are harsh, and i am sure you didn't check the PCB version of each of your kit
It can be that these are on a different PCB (both sets) and just not plugged in the correct place
Yes, your timings are harsh ~ try something a bit more tame and first push FCLK & fix the voltages ,before you push both
Especially when 5xxx series does autocorrect on everything and slow itself down to prevent crashes

This two docs have "patterns" for you to copy
&

CAD_BUS you should start with 40-20-20-20
maybe go up to 60-20-20-20 with 4 dimms

RTT is up to you to figure out with 4 dimms
try maybe if 7 / 0 / 6 works also for 4 dimms ~ but this one requires you to move near 1.47+ VDIMM , even 1.48+
Figuring out which PCB these kits are on, running a lose 16-16-16 set to figure out voltage & procODT
all these should be your first priority before you land in a deep rabbit hole of autocorrection
Crashing Vermeer is very very hard , but making it unhappy is as easy as just 20mV wrong voltage ~somewhere~

EDIT:
I would also try to CMOS reset & go back to 1800FCLK
There are bugs where 2:1 mode is turned on in the hidden
61ns on Vermeer, equals about 71-72ns on Matisse
Either something is strongly autocorrecting and slowing itself down
Or you have the 10ns 2:1 mode penalty in there

It's a bit too slow for your used timings - soo something is clearlywrong
Also F31f is a bit slow - visible on t he old SMU 56.40
You can stay on this - if gigabyte also has no FCLK limits on it
Or try your luck and update to F31o or higher ~ just with the likelyhood of being limited beyond 1900FCLK


3 passed loops with all tests. 3x 18min
at best 4x18

it should already FFT & N32 crash on the first loop if voltages are wrong
or on the 2nd loop if your VRMs droop too much by heat ~ as an LLC issue
Thank you for the response. The PCB of my ram chips are: K4A8G085WB-BCPB which match up with the majority of those on the google sheets page.
I did a CMOS reset and went to loose timings (16-16-16 at FCLK 1800). I set VDIMM at 1.45v and left everything else auto. I get about 65.4ns.
The RTT values I was using came from the DRAM calc, but it sounds like that is not correct. I have been following the patterns from the google sheet. Trying to find someone with 4x8 single rank running at 3733. Even when I can boot with their settings I am still in the >61ns range for latency.
I am wondering if it is a Bios thing. Gigabyte posted the final version of F31 on Dec 9, 2020. That is what I have been using. Before that I was on F31j and that seemed pretty stable too. With this final version of F31, I am still getting WHEA errors when I set FCLK to 1900. So maybe I need to wait for the next bios or stay at F31j.
 
@Veii

I'm currently on an old Gigabyte bios, F22.
SMU 46.62.00

In my AMD CBS sub menu I have NBIO Common Options with another sub menu called SMU Common Options.

Another AMD CBS sub menu option I have is called Soc Miscellaneous Control which offers
ABL Console Out Control = Auto
ABL Basic Console Out Control = Auto
ABL PMU message Control = Auto

I don't know what ABL version I'm on ?
 
@Veii

I'm currently on an old Gigabyte bios, F22.
SMU 46.62.00

In my AMD CBS sub menu I have NBIO Common Options with another sub menu called SMU Common Options.

Another AMD CBS sub menu option I have is called Soc Miscellaneous Control which offers
ABL Console Out Control = Auto
ABL Basic Console Out Control = Auto
ABL PMU message Control = Auto

I don't know what ABL version I'm on ?
Ah oke oke, yes you are on Matisse
ABL console out is for debugging purposes only ~ i see nothing that makes good usage out of it
As long as you have UncoreOC mode enabled - the voltages will be applied,soo it likely is an issue of too much strain ala bad signal integrity or just high voltages and high proc

SMU common options for you should have CPPC and CPPC preferred cores
nah not helpful
If you use PBO, you can try and limit SOC TDC & SOC EDC to 13A & 15A
Idk how to help you here. Maybe you trigger some OCP or fabric crashes
It needs more debugging. Can't figure your issue out with this information
 
@Veii Yes, I'm still on Matisse. I have updated to bios F31 so I'm back to square 1. I should just drop in my 5800X and completely start from the beginning, although I'm kinda holding out for AGESA 1180...

So F31 SMU 46.65.00

TM5 crashed and is now only showing 6 tests (0-5)... what do i change in the cfg file again? I still have it set for 25 cycles
 
Thank you for the response. The PCB of my ram chips are: K4A8G085WB-BCPB which match up with the majority of those on the google sheets page.
I did a CMOS reset and went to loose timings (16-16-16 at FCLK 1800). I set VDIMM at 1.45v and left everything else auto. I get about 65.4ns.
The RTT values I was using came from the DRAM calc, but it sounds like that is not correct. I have been following the patterns from the google sheet. Trying to find someone with 4x8 single rank running at 3733. Even when I can boot with their settings I am still in the >61ns range for latency.
I am wondering if it is a Bios thing. Gigabyte posted the final version of F31 on Dec 9, 2020. That is what I have been using. Before that I was on F31j and that seemed pretty stable too. With this final version of F31, I am still getting WHEA errors when I set FCLK to 1900. So maybe I need to wait for the next bios or stay at F31j.
K4A8G085WB-BCPB is the model number of 1024mb 20nm B-Dies :)
4x 1024 put together left , and 4 on the right
The real PCB you have to figure out in person
Here is a repost of all 3 shematics. I miss the A3 Shematic sadly
2468995

2468996

2468997


A0 is easy to recognize, by the location of the ICs
A1 & A2 depend on the notch at the bottom

Corsair Vengeance Pro appears to use a custom A1 PCB without the little cap over the notch
Viper Taiwan (steel series) uses a custom A2 PCB on their 4400 series, and A0 on their 4000 series

Many timings and settings depend on the PCB version ~ many hardlimits and voltage limits
It could be a Bios thing - which you can try to resolve by using something pre-patch C, like i do
1800 CL16-16 should be in the 54ns region. Maybe you have bugs to push you to 2:1 mode
It would make sense latency wise, as it does add 10ns on it
 
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