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[Official] AMD Ryzen DDR4 24/7 Memory Stability Thread

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#24,701 ·
WereCat said:
@ApT01 I think it comes down the variability in your test methodology. I found that Ryzen is quite sensitive to temp which results in clock stretching so on cold boots I tend to score best results since my AIO water is cold which will skew results for first batch of benchmarks and will make them seem like they are better even though they are worse because the score will gradually go down as the cooler approaching the steady state so all benching results will be invalid. I also did all test in Windows Safe mode as I found it to have very consistent results (for these particular benchmarks, many other stuff will not even run there).
That's why I bothered to blast Linpack for many loops before doing benchmarking for this. Only thing I can't control is my room temp. All the results are also listed in the order I tested them so the room was also getting gradually warmer.
Click to expand...
Thats the thing right, I tested Linpack with each set of timings sequentially having plenty of time inbetween runs, so heat soak can't be the issue. And I use a stripped LTSC install so background processes wouldn't interfere. Have you done any benching at tRAS 21, tRC-54 ?
 
#24,702 ·
ApT01 said:
Thats the thing right, I tested Linpack with each set of timings sequentially having plenty of time inbetween runs, so heat soak can't be the issue. And I use a stripped LTSC install so background processes wouldn't interfere. Have you done any benching at tRAS 21, tRC-54 ?
Click to expand...
I have't tried yet. Right now I'm testing for stability which will take quite a bit of time on 64GB, got an error at 4000% coverage when I left it over night so I increased tRP from 14 to 16 as I suspect that's the one causing issues as before I also got some errors in y-cruncher when doing 10B with this timing at 14.
 
#24,704 ·
ManniX-ITA said:
Sporadic error #12 is also sometimes tRTP/tWR try with 8/16.
Also linked to tRCD, try to set tRCDWR to 10.



tRFC and tRCD are purely depending on IC quality and voltage.
You need more voltage for the 1T config and this limits your tRFC.
If you can't run tRCDRD at 14 with that voltage is unlikely you can lower it.

Very likely if you raise the VDIMM it will be hard to stabilize.
It's already pretty good for a 4 x SR configuration.



Did you disable the cache on Kahru?

No errors on TM5 and a single error on Kahru smells like you left it enabled and there's an issue with the CPU.
Even if you have a very good 5900X sample, the VSOC can be a problem.
Test if you can pass with a slight bump up from 1.1V.
Click to expand...
Just wanted to say thank you again for the tips, you were correct on both accounts.
I so far still haven't had much luck with straight 14's but did test and stabilize the 240 tRFC.

System needed just a single bump to SOC (1.112 to 1.11875) to stabilize a 280 tRFC .
Core 0 needed to be lowered -23 to -22 C.O. to stabilize the 240.
Passes 20 hrs Kahru, 2 X 25 cycle runs TM5, a 9 hr then a 6 run of YCruncher so far.

Any chance there's anything left performance wise?


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#24,705 ·
The Sandman said:
Just wanted to say thank you again for the tips, you were correct on both accounts.
I so far still haven't had much luck with straight 14's but did test and stabilize the 240 tRFC.

System needed just a single bump to SOC (1.112 to 1.11875) to stabilize a 280 tRFC .
Core 0 needed to be lowered -23 to -22 C.O. to stabilize the 240.
Passes 20 hrs Kahru, 2 X 25 cycle runs TM5, a 9 hr then a 6 run of YCruncher so far.

Any chance there's anything left performance wise?


View attachment 2652756
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Unless you go higher FCLK or can get off using ACS Setup 56 or drop RCDRD to 14 not much more to tighten, overall pretty solid for a 4 X dimm setup.

Here is mines using 2 X 8GB setup never ran more than 10 cycles because I was not going run this on a daily basis running 3800 CL15-15-15 only needs 1.40V which is what I ran
most of the time. 3866 CL15 needs only 1.45V which may be better to run for a daily setup than 3800 CL14 with +1.5V. If you can get it stable without WHEA errors.

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3866 CL15 @ 1.45V
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3800 CL15 @ 1.4V short test but these timings are easy peasy for Samsung B-die.
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#24,706 ·
The Sandman said:
Any chance there's anything left performance wise?
Click to expand...
That's indeed pretty good already :)

You should be able to use tWRWRSCL at 2 to gain some hundred megabytes on write and copy.
Maybe experiment with some aggressive SC/SD/DD settings but, honestly, could be a gigantic pain for almost nothing.
 
#24,707 ·
So I passed 13h and 12,000% coverage of Karhu RAM Test, I passed 100 iterations of y-cruncher VT3 and then I keep consistently getting errors within the first 3 to 5 iterations of y-cruncher FFT. I've now spent almost entire day loosening timings, tweaking various settings and voltages and for sanity check I decided to try all auto without DOCP and that seems to work fine...

Recently found out that it seems like upping DRAM voltage or significantly loosening tCL helps a lot but I'm still not stable. Right now I just passed 10 iterations of FFT with +100mV of DRAM to just get error few minutes later so now I'm testing again at 1.48V (another +50mV).

I've never used y-cruncher before for stability testing so otherwise I would consider my OC to be stable enough but this FFT test seems really demanding on DRAM. Not sure how well it represents normal system usage and if it's worth to shoot for complete FFT stability.

The biggest issue here is that it seems like I can't drop down to CL15 but have to go all the way to CL16 in the worst case scenario as that messes the whole tCWL, tRDWR, tWRRD timings and I can't get my system to even boot unless I disable GDM and switch to T2 (which forces tCL to 16 anyways).
 
#24,708 · (Edited)
WereCat said:
So I passed 13h and 12,000% coverage of Karhu RAM Test, I passed 100 iterations of y-cruncher VT3 and then I keep consistently getting errors within the first 3 to 5 iterations of y-cruncher FFT. I've now spent almost entire day loosening timings, tweaking various settings and voltages and for sanity check I decided to try all auto without DOCP and that seems to work fine...

Recently found out that it seems like upping DRAM voltage or significantly loosening tCL helps a lot but I'm still not stable. Right now I just passed 10 iterations of FFT with +100mV of DRAM to just get error few minutes later so now I'm testing again at 1.48V (another +50mV).

I've never used y-cruncher before for stability testing so otherwise I would consider my OC to be stable enough but this FFT test seems really demanding on DRAM. Not sure how well it represents normal system usage and if it's worth to shoot for complete FFT stability.

The biggest issue here is that it seems like I can't drop down to CL15 but have to go all the way to CL16 in the worst case scenario as that messes the whole tCWL, tRDWR, tWRRD timings and I can't get my system to even boot unless I disable GDM and switch to T2 (which forces tCL to 16 anyways).
Click to expand...
I like TM5 with 1usmus_V3 profile for testing because you can use this spreadsheet to decipher errors codes. Something other test don't do AFAIK so they seem like a waste of time for me.

docs.google.com/spreadsheets/d/1MTKvkEI5mXchE_XFaiG9AAS89sOANAy7YY69bWLkdQ8/

You may be getting errors in some tests because tRP is low hence RC is too low and you are missing data or the recent SCL changes you made.

I would suggest to retry but without the lowering tRP and leaving both SCLs at 4. Let tRP=RCDRD=RCDWR 20 20 20 and adjust tRC accordingly

The only two tests I use to test system stability is 25 cycles of TM5 using 1usmus_V3 profile which is enough and more the 50 cycles is just overkill and pointless IMHO.

The other test that I would use is 1 hour of OCCT AVX2 Variable Large Extreme. If it passes these two tests I consider the system to be stable with the tested RAM or CPU OC.
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#24,709 · (Edited)
@The_King
Thanks, will give TM5 a try, I'm not familiar with it at all. I used to use OCCT in the past but it never worked out well for me, will give it a go now as well as it seems that it has changed a lot since then.

I should have provided screenshots as well but I was posting from another device so had no access to them but there it goes...

You're right that tRP 14 was too low, I got an error at around 4000% coverage before and upped it to 16 and this seems to be fine now. Also I've loosened all those timings you've mentioned and still got errors in FFT until I upped DRAM voltage. (tried as low as 22/22/22 for the RCDRD/RCDWR/RP)
Now I passed 50 iterations with 1.48V DRAM (Karhu and VT3 passed at 1.46V) and did a one tick bump up to SOC as well.

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To be honest I've spent all this time on 3600MT/s since last Saturday and I'm really tired of running countless test and want to finally move on to 3800MT/s so I think I'll call this stable enough for now and will do TM5 and OCCT at 3800MT/s after a day or two break. Though considering how much voltage FFT takes to get stable at 3600MT/s I think I'll have to go quite a bit higher at 3800MT/s and I hope I can keep it at tCL 14 as well because getting tCL 15 to boot is a huge pain due to tCWL/tRDWR/tWRRD. I know I can boot tCL 14 at least at 3800MT/s but never got it quite stable before.

edit:
oh and btw, this is not a single kit of 4x16GB DR but two kits of 2x16GB DR.

edit2:
and I still haven't tested performance difference between different interleaving sizes, want to do that as well.
 
#24,710 ·
Hi guys

I have spent now some days, to find a setup running and am surprized, that 2x32 DR runns 1T GDM OFF at 3800 MT/s with just 1.3v. y-cruncher VT3 and TM5 anta777 extreme stable.

would be great, if somebody can give me his lights, if everything is right, or if I have something to change. CL16 works with 1.45v. RCDs 18 just refuse to work error free. I prefere to have low voltage with 18-19-19.

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#24,711 · (Edited)
Unifyx said:
Hi guys

I have spent now some days, to find a setup running and am surprized, that 2x32 DR runns 1T GDM OFF at 3800 MT/s with just 1.3v. y-cruncher VT3 and TM5 anta777 extreme stable.

would be great, if somebody can give me his lights, if everything is right, or if I have something to change. CL16 works with 1.45v. RCDs 18 just refuse to work error free. I prefere to have low voltage with 18-19-19.

View attachment 2652936
Click to expand...
Do you know what IC is in the kit? Micron Rev.E?

Since GDM is disabled have you tried CL 17? Stock XMP is usually 1.35V so if you can get CL17 with that or less it should be perfectly fine for a daily setup.

if it is Micron I would try to run at CL15 @ 1.45V that should drop tPHYRDL to 26.

If you happy with CL18 then not much to change if you increase tCWL to 18 you should be able to drop RDWR to 10 or 9.

tCWL should equal tCL for best stability unless tCL is odd then tCWL can be tCL-1.

Save your OC profile before making changes in the BIOS. Sometimes setting the wrong tRDWR will cause the system to hang.


WereCat said:
@The_King
Thanks, will give TM5 a try, I'm not familiar with it at all. I used to use OCCT in the past but it never worked out well for me, will give it a go now as well as it seems that it has changed a lot since then.

I should have provided screenshots as well but I was posting from another device so had no access to them but there it goes...

You're right that tRP 14 was too low, I got an error at around 4000% coverage before and upped it to 16 and this seems to be fine now. Also I've loosened all those timings you've mentioned and still got errors in FFT until I upped DRAM voltage. (tried as low as 22/22/22 for the RCDRD/RCDWR/RP)
Now I passed 50 iterations with 1.48V DRAM (Karhu and VT3 passed at 1.46V) and did a one tick bump up to SOC as well.

View attachment 2652879

View attachment 2652880

View attachment 2652881

To be honest I've spent all this time on 3600MT/s since last Saturday and I'm really tired of running countless test and want to finally move on to 3800MT/s so I think I'll call this stable enough for now and will do TM5 and OCCT at 3800MT/s after a day or two break. Though considering how much voltage FFT takes to get stable at 3600MT/s I think I'll have to go quite a bit higher at 3800MT/s and I hope I can keep it at tCL 14 as well because getting tCL 15 to boot is a huge pain due to tCWL/tRDWR/tWRRD. I know I can boot tCL 14 at least at 3800MT/s but never got it quite stable before.

edit:
oh and btw, this is not a single kit of 4x16GB DR but two kits of 2x16GB DR.

edit2:
and I still haven't tested performance difference between different interleaving sizes, want to do that as well.
Click to expand...
Running tCWL at 12 can be the cause of stability issues. Yes it benchmarks faster but can cause lots of headaches.

Make sure its set to TCWL to 14 if you running CL 15.

If you going to try for 3800 CL14 then tCWL should also be 14 because 12 will make it harder to stabilize.
It is tricky to run 3800 CL14 on my Micron kits has well and usually needs much more voltage compared to 3800/3866 CL15.

By increasing tCWL to 14 you could probably drop tRDWR to 8 in your current 3600MT CL14 setup.

3800MT may need higher tRDWR like 9 or 10 have to test which is stable. Running 3800MT with too low tRDWR like 8 may cause the system to hang.

My current kit daily setup timings to give you an idea of what is 100% stable for me.
Forgot to drop CLDO VDDP in the first one it was left on Auto should be 0.95V.
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#24,712 ·
The_King said:
Do you know what IC is in the kit? Micron Rev.E?

Since GDM is disabled have you tried CL 17? Stock XMP is usually 1.35V so if you can get CL17 with that or less it should be perfectly fine for a daily setup.

if it is Micron I would try to run at CL15 @ 1.45V that should drop tPHYRDL to 26.

If you happy with CL18 then not much to change if you increase tCWL to 18 you should be able to drop RDWR to 10 or 9.

tCWL should equal tCL for best stability unless tCL is odd then tCWL can be tCL-1.

Save your OC profile before making changes in the BIOS. Sometimes setting the wrong tRDWR will cause the system to hang.
Click to expand...
I think they are M16B micron rev-b.

XMP is 3600 MT/s 16-19-19-39 @ 1.4v and they can do 4200 MT/s flat 20 @ 1.45v ( didnt try 18-20-20 ) so that it cant be M16E micron rev-e.

will try CL17 tomorrow. If it works, perfect! Otherwise I try to change tCWL to 18 with RDWR to 10 or 9.

Thanks for your help. 😊
 
#24,713 ·
an update:

CL17 or 16 doesn't work. It hangs while training at number 61 or 62, even with 1.45v. I think it's because of 1T GDM off. 1T GDM ON at CL16 works but is slower than 1T GDM off at CL18.

Funny thing is testing y-cruncher 2.5b all at 18-19-19-39
1T GDM ON : ~82.5s
2T GDM off : ~81.5s
1T GDM off : ~80.3s

So I think I stay with the CL18-19-19-39@1.3v
1T GDM OFF.
 
#24,714 ·
ManniX-ITA said:
That's indeed pretty good already :)

You should be able to use tWRWRSCL at 2 to gain some hundred megabytes on write and copy.
Maybe experiment with some aggressive SC/SD/DD settings but, honestly, could be a gigantic pain for almost nothing.
Click to expand...
I will be glad to receive any suggestions on tightening timings for the frequency 3400?
I believe that by lowering the CLDO_VDDP and increasing the SOC voltage a little bit, we managed to achieve stability. My next goal is to go to tCL 15(14) with accompanying primaries. By the way, I put RC and RP on the recommendation of The_King for Micron E (thanks to him for that) After all, Nanya is a daughter bought by Micron, as far as I know.
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#24,715 ·
The_King said:
Running tCWL at 12 can be the cause of stability issues. Yes it benchmarks faster but can cause lots of headaches.

Make sure its set to TCWL to 14 if you running CL 15.

If you going to try for 3800 CL14 then tCWL should also be 14 because 12 will make it harder to stabilize.
It is tricky to run 3800 CL14 on my Micron kits has well and usually needs much more voltage compared to 3800/3866 CL15.

By increasing tCWL to 14 you could probably drop tRDWR to 8 in your current 3600MT CL14 setup.

3800MT may need higher tRDWR like 9 or 10 have to test which is stable. Running 3800MT with too low tRDWR like 8 may cause the system to hang.

My current kit daily setup timings to give you an idea of what is 100% stable for me.
Forgot to drop CLDO VDDP in the first one it was left on Auto should be 0.95V.
View attachment 2652937 View attachment 2652938
Click to expand...
tCWL = 12 works fine. It's tCWL = 14 that is an issue.

I can't boot with tCWL = tCL unless I have tRDWR = 18 and tWRRD = 7 when GDM is OFF.
At tCL 14 and 16 I must maintain tCWL = tCL - 2 or it wont boot.
This means that tCL 16 works with tCWL 14 but... tCL 15 will not boot with tCWL 14 and dropping it to 13 does not work either.

And as I've already mentioned before, I can't boot with any other combination of tRDWR / tWRRD besides the default 18/7 and my 10/1 as I've already tried all combinations.


I've tried today and I can't seem to get 3800MT/s with GDM OFF to work which means I can't get tCL 15 to work and have to drop all the way down to tCL 16 with some other major sacrifices to secondaries.
I can boot 3800MT/s tCL 14 at 1.525V DRAM but even at 1.55V it's not stable and I don't feel like it's worth it to even try more for daily use at this point so right now I'm testing 3733MT/s with GDM OFF which seems to work fine with almost the same timings as my 3600MT/s OC... but at 1.54V DRAM. Kinda on the edge of what I'd call dailyable for rev. E but I've already tried 1.535V and it's not stable.

I have not tried tweaking ProcODT yet. If I understand it correctly lower ProcODT should allow me to use less voltage at the cost of max achievable clock speed... is that right? (not sure how it affects stability of timings) Maybe it's worth a shot to try in the 32-40ohm range instead of the AUTO = 43.6ohm I have right now.

I'll finish my stability testing and then I'll decide if I want to daily this or just keep it for benching.
 
#24,716 ·
WereCat said:
tCWL = 12 works fine. It's tCWL = 14 that is an issue.

I can't boot with tCWL = tCL unless I have tRDWR = 18 and tWRRD = 7 when GDM is OFF.
At tCL 14 and 16 I must maintain tCWL = tCL - 2 or it wont boot.
This means that tCL 16 works with tCWL 14 but... tCL 15 will not boot with tCWL 14 and dropping it to 13 does not work either.

And as I've already mentioned before, I can't boot with any other combination of tRDWR / tWRRD besides the default 18/7 and my 10/1 as I've already tried all combinations.


I've tried today and I can't seem to get 3800MT/s with GDM OFF to work which means I can't get tCL 15 to work and have to drop all the way down to tCL 16 with some other major sacrifices to secondaries.
I can boot 3800MT/s tCL 14 at 1.525V DRAM but even at 1.55V it's not stable and I don't feel like it's worth it to even try more for daily use at this point so right now I'm testing 3733MT/s with GDM OFF which seems to work fine with almost the same timings as my 3600MT/s OC... but at 1.54V DRAM. Kinda on the edge of what I'd call dailyable for rev. E but I've already tried 1.535V and it's not stable.

I have not tried tweaking ProcODT yet. If I understand it correctly lower ProcODT should allow me to use less voltage at the cost of max achievable clock speed... is that right? (not sure how it affects stability of timings) Maybe it's worth a shot to try in the 32-40ohm range instead of the AUTO = 43.6ohm I have right now.

I'll finish my stability testing and then I'll decide if I want to daily this or just keep it for benching.
Click to expand...
I did not see you had an 5800X3D many of those CPU have issues with FCLK 1900 if you can boot then you one of the lucky ones. Many not all 5800X3D have a FCLK 1900 hole.

Also running 4X16GB DR dimms is very hard on the IMC so your 3600 CL14 results is actually great. (y)
 
#24,717 · (Edited)
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This is my current setup with 4x8 CJR. After several runs with Hydra at various voltages and speeds, this is where I settled.
Additionally, my struggle with stabilizing the L3 cache/voltages using AIDA was self-inflicted by using a very outdated version, because it had a license.

I am not sure there is any benefit from dropping RCDWR or CWL? I don't see any discernible differences in benchmarks.


I should add that I used Hydra for the CO values at +200, and for the first time that runs stable. Previously limited to +50. I think 1usmus has been doing a great job with that project.
 
#24,719 ·
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I reset the voltages to +.001. At VDDP .900, PHYRDL goes to 28 on bank A. At .901, it keeps 26/26. It passed through the night....so I am happy.
I have tried this RAM through many voltages and many speeds with Hydra. Though, Hydra does force a different set of RTT values. It would be interesting, to me at least, if I could run the Hydra scan while using the RTTs that work most stably with my motherboard/RAM. I am not 100% certain that is why anything above 3800 results in higher latency, or if that is just my RAM needing extra loosening above 1.4V. This is with 1.39V. Back to the RTTs, my motherboard AUTO's them to 7-2-1, and running through TM5 1usmus with Veii's error chart is what brought me there...though it aligns with the DRAM calc settings for 4 sticks of DR. Just a quirk of my setup?
 
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